Subscribe to Our Digest
By Patrick Mannion, Data Centre Digest Contributing Editor
In part one of this series, we discussed the need to shift to a holistic silicon-to-system design approach for AI data centers. In part 2, we examine why and how cutting-edge design tools are accelerating this shift.
Artificial intelligence (AI) workloads are exposing the limits of traditional semiconductor and system design. As AI processors push the limits of bandwidth, power density, and integration, electrical, thermal, mechanical, electromagnetic, and optical behaviors are increasingly interdependent. The traditional approach of analyzing and optimizing these domains largely independently and compensating for their interactions with conservative design margins is becoming too costly in terms of performance, power consumption, silicon area, and design time. Increasingly, the industry needs to consider replacing this “overdesign” with system-level co-design.
“It’s not just about designing a chip,” said Hany Elhak, Executive Director of EDA Product Management at Synopsys. “While you’re designing the chip in the electrical domain, you’re also measuring and analyzing what happens in the optical, electromagnetic, power, thermal, and mechanical domains.” That observation reflects a broader shift across semiconductor engineering. As AI systems become more tightly integrated, designers are no longer optimizing individual components in isolation; they are increasingly co-optimizing interactions across the entire system.
One of the clearest examples of this convergence is the move toward PCIe 8-class interconnects (Figure 1). At 256 giga-transfers per second (GT/s) per lane, maintaining signal integrity extends well beyond traditional electrical design considerations. Power integrity, thermal effects, advanced packaging, board materials, and electromagnetic behavior all influence link performance. This is one reason photonic technologies, including co-packaged optics (CPO), are attracting increasing attention as a means to meet future scale-up and scale-out bandwidth and efficiency requirements.
Rather than representing separate engineering challenges, these once-separate domains are converging into a single system-level design problem that conventional design methodologies were never intended to address. This growing convergence is forcing fundamental tools, such as electronic design automation (EDA), to evolve.
The concept of multiphysics analysis is not new. Traditionally, each physical domain has been analyzed largely in isolation, with designers completing much of the physical implementation before running separate thermal, electromagnetic, mechanical, or power-integrity analyses to validate the design and identify potential issues (Figure 2). If issues emerged, the design entered another optimization cycle, often requiring conservative margins to account for uncertainties across the various analyses.
However, as AI drives higher bandwidth, greater power density, advanced packaging, and faster interconnects, interactions among the electrical, thermal, mechanical, and optical domains have become more tightly coupled (Figure 2). Consequently, sequential analysis has become increasingly inefficient, necessitating repeated design iterations and conservative guardbands. These guardbands increase power, area, and cost at a time when designers are under pressure to do the opposite.
Complicating matters is the need to perform multiphysics analysis across multiple disparate toolchains, slowing the process and opening the door to data handoff and translation errors.
What’s required goes beyond more accurate or faster tools. Design tools must bring multiple physical domains into the design loop, allowing designers to evaluate interactions as they occur rather than after the fact. That is the principle underlying Synopsys’ Multiphysics Fusion platform.
A good example of the required shift toward co-design is the recently announced Multiphysics Fusion solution, which integrates Synopsys AI-powered design platforms with Ansys proven multiphysics analysis across the entire design flow. This unified architecture enables more consistent system-level insight, reduces correlation gaps, and improves predictability from early design through signoff.
The result is faster convergence and improved power, performance, and area (PPA) through 3x faster signoff, 10x faster design closure, 10x faster photonics simulation, and faster multi-die design (Figure 3).
According to Synopsys’ Elhak, designers using Multiphysics Fusion can reduce the area of a $725 million chip design by up to 35%, which translates to $250 million in savings. Again, this is theoretical, as he acknowledges that designers tend to add more functionality wherever possible.
The rise of platforms like Multiphysics Fusion reflects a broader industry recognition that AI is changing not only what engineers design but also how they design it. As systems continue to push the limits of bandwidth, power density, packaging complexity, connectivity, and photonic integration, engineering disciplines that once operated independently are becoming inseparable. Concurrent system-level co-design at the chip, package, and interconnect levels, enabled by AI-powered frameworks, is an important step toward eliminating overdesign and improving PPA. But it is only one part of a much larger transformation.
Breaking AI’s next-generation bottlenecks will ultimately require extending the same co-design philosophy across the entire computing stack, from silicon and connectivity to boards, racks, power delivery, cooling, networking, and software.